Historically, integrated circuit designs have been driven to smaller feature sizes and increased integration density by the incentives of improved performance, increased functionality on a single chip and reduced cost of manufacture. For example, smaller device sizes and increased proximity reduces signal propagation time, allowing higher clock speeds and reduced susceptibility to noise while providing for more devices that can be formed with a given sequence of processes on a single chip and which are thus available to perform more complex and or more numerous functions concurrently.
Throughout the development of integrated circuit devices, device size and density on an integrated circuit chip has been limited by the ability of lithographic processes to produce patterns in a resist or hard mask with sufficient accuracy of shape/critical dimensions and sufficient reliability to support acceptable manufacturing yield. However, state of the art semiconductor designs and processes are approaching the theoretical limits of optical lithography to the point where a single optical exposure can no longer be used to pattern a given single wafer level; largely due to diffraction effects at apertures in optical masks and radiation scattering effects in a resist. Optical diffraction and scattering effects cause partial exposure of a resist in the vicinity of the intended area of exposure as well as distortion of the intended exposure pattern or shape and, since resist exposure is cumulative, exposure of features in close proximity to each other can increase distortion, alter size and may even cause additional patterns to be exposed. Variation of resulting feature shape from desired feature shape may also be caused by characteristics of a process such as etching or resist development for forming the desired structures.
To address the problems related to exposure which are collectively referred to as optical proximity effects, a process (that is not admitted to be prior art in regard to the present invention) involving a sequence of resist exposure and development processes has been used to build up the desired pattern of features in a hard mask by using a sequence of patterned exposures where features are much less proximate to each other than in the final design. Such a process can use as many lithographic exposure and development processes as necessary to reduce optical proximity effects to an acceptable level or to avoid them altogether and will be referred to hereinafter as multiprocess patterning. However, such processes may also be referred to as double expose, double etch processes, split pitch processes or the like even when the number of exposure and etch sequences is not limited to two. The completed hard mask is then used to transfer the desired pattern into underlying semiconductor material by etching or the like. However, such processes do not correct or even consider feature distortions due to material removal processes and are very limited in capacity for assuring fidelity of the semiconductor device features to the original integrated circuit design.